Design Guidance for Problem 2.13

Usually, the most important specification for a functional block such as an oscillator is the required power output into the load.  In this case, the requirement is 11.7 mW into a 50 ohm load, via a 4:1 transformer.  This load can be transformed to the primary side of the transformer where it will appear as 800 ohms across the tank circuit.  It is this transformed 800 ohms  which must dissipate the 11.7 mW.

Determining Emitter Bias Voltage

In order for this to happen, the collector circuit must provide an RMS voltage of :

VRMS = (.0117*800)1/2 = 3.06 VRMS  or 4.33 volts (0-Peak)

It is customary to design for a safety margin of, say 20%, so let's design for an AC voltage amplitude Vce =   5.2 volts (0-Peak).  Since the collector is biased through the transformer primary at VC = Vcc = 10 VDC (with respect to circuit ground), the maxumum instantaneous collector voltage  must be vC(max) = 15.2 volts, and the minimum will be  vC(min) = 4.8 volts.  This is illustrated by the voltage waveform on the graph below.  The emitter bias voltage must therefore be chosen to be slightly lower (say, one volt) than the minimum collector voltage in order to prevent saturation when the collector voltage swings to it's minimum value, yielding a design DC emitter voltage of VE = 3.8 volts.

Determining Collector Bias Current

The collector DC bias current IC  must accommodate the maximum required peak AC collector current Ic without going into cutoff when driving the total collector load with an AC voltage Vce =  5.2 v (0-peak).  The collector load consists of the transformed 800 ohms, in parallel with the transformed feedback resistance, in parallel with the parasitic resistance of the coil (which we will have to neglect, since its Qu is not given), and the dynamic collector resistance rC(which we shall also neglect since it is not given).  Since we don't yet know IC, we can't calculate re, so we'll use a worst case value of zero ohms for re and set the feedback resistance equal to the crystal resistance, or 10 ohms.  This is applied to the collector via a 10:1 voltage divider, yielding a collector resistance contribution of 1000 ohms from the feedback circuit.  Total collector AC resistance Rc' is therefore 1000 in parallel with 800 or Rc' = 444 ohms.  This load will draw an AC current  Ic = 11.7 mA (0-Peak) whenVce =  5.2 v (0-Peak).  The collector bias current level must be chosen to supply this peak AC current without going into cutoff; therefore we should  provide for a collector bias current of at least  IC = 11.7 mA DC.  Allowing for a safety margin of, say 20%, this results in a design DC bias current of  IC = 14 mA.

The resulting total collector voltage and current waveforms for one cycle is shown on the graph below.
 


 
 

Once Emitter voltage and collector (~ emitter) current bias points are determined, the biasing resistors may be chosen. Since we designed with considerable safety margins, we can pick our values from standard resistor values.   It only remains to verify that, with these choices, the resulting gain is sufficient to sustain oscillations, and the minimum load power requirement is met.

With the given capacitor divider, you should compute a loop voltage gain of approximately 3.5 (~11 dB), which is a little high.  This means the transistor gain must compress by 11 dB for stable operation (loop gain = 1, or 0 dB), which will cause substantial clipping and distortion in the output waveform, and resultant harmonic generation.  For 5 points extra credit, modify the design to provide a loop gain of 3 dB.